1. Field of the Invention
The present invention relates in general to highspeed computers, and relates in particular to a computer for processing a large volume of data such as image data and other multimedia applications, and an integrated circuit memory designed for improved speed of processing to be used with the computer.
2. Description of the Related Art
An example of the configuration of a conventional small computer is shown in FIG. 8. Mathematical computation and signal processing are performed by combined actions of a microprocessor 1 connected to the main memory 2 by way of a bus.cndot.memory controller 3. Input data are supplied from an input/output (I/O) device 5, through a system bus 7, to the bus.cndot.memory controller 3. The I/O device 5 is connected to a communication port (comport) 8, and performs data transmitting and receiving tasks for the communication circuit and the computer.
The I/O device 5 is connected with secondary memory devices 10, such as hard disk and floppy disk, and input devices 11 such as a keyboard and a mouse. The results of computations generated by the microprocessor 1 are supplied, through the system bus 7, to the video controller 4, and are stored in a frame buffer 9. The data stored in the frame buffer 9 are displayed in real time on a monitor 6 under the control of the video controller 4. The frame buffer is a type of (semiconductor) memory for storing current data.
FIG. 9 shows another example of the system configuration of a conventional computer. In this example, instead of storing the data in the frame buffer 9 connected to the video controller 4, the current image data are stored in a section of the main memory 2. The components other than the frame buffer, such as input section and computation section, are the same as those shown in FIG. 8. The cost of the system is reduced because of lesser number of required component parts.
The circuit components used for main memory 2 and frame buffer 9 are integrated circuits, such as the one shown schematically in FIG. 10. The data are stored in memory cell array 20 comprised by several mega bits to several tens of mega bits of memory cells. A memory cell is specified by an address in the memory cell array. An address is given in the binary notation from the address port 27, and an address decoder 21 is used to specify a memory cell or a group of memory cells. Data are written into the memory cells from the data port 26, by way of a buffer 23. The contents of the memory are read by the sense amplifier 22, and are output to the data port.
To improve the output speed of the video data, a dedicated integrated circuit, a video RAM, is sometimes used for the frame buffer. As illustrated in FIG. 11, such an IC memory stores a group of data read out by the sense amplifier 22 in the data buffer 32, and reads the data from the data buffer 32 one bit at a time from the data port 26' according to an address signal prompted by a counter 33 operating at the clock frequency generated by clock input means 34. The data port 26' serves as the data output terminal to the monitor 6.
As shown in FIG. 12, a computer system having a dedicated video memory is assembled so that the monitor 6 is connected to the frame buffer 9 by way of an digital-to-analogue converter (D/A converter) 12. Incidentally, normally an D/A converter 12 is included in the video controller 4, but the D/A converter 12 is shown separately from the video controller 4 in FIG. 12, because such an integral dedicated memory has a separate video output port, as in the example in FIG. 12.
There is much demand for decompressing of compressed image data for display, because of the significantly high volume of data signals required for image processing, and high signal processing performance is requested.
The process of decompressing the compressed image data signals, according to specifications by Motion Picture Engineers Graphics (MPEG), will be explained with reference to a flowchart shown in FIG. 13. The image signals delivered from a communication circuit or a recording medium are separated into image data component, motion vector components and quantizer indexes, in the signal separation task 50. The image data are already encoded into variable-length words according to such methods as Huffman encoding, for example, and are decoded in the variable-length word decoding task 51. In the reverse quantization processing task 52 which follows, the original signals are restored using the quantizer table. The quantizer table is included in the delivered signals, and are separated during the process of signal separation. Afterwards, in the inverse quantization cosine conversion (DCT) task 53, the frequency components are converted to real space components. At this stage, frame-to-frame sequence data are processed using the motion vector (obtained in the signal separation task 50) in the motion compensation task 56, and then the sequence data are added in the adder 54 to the image data processed by the DCT processing task 53, to restore the original images. Finally, the rearranging processing task 55 rearranges the image data in the chronological sequence, to restore the true image data from the compressed image data. The restored data are delivered, as new image data, to the image accumulation processing task 57 and form the basis for compensating the next image movement.
In the computers shown in FIGS. 8, 9 and 12, the image processing is performed as follows. First, image data are input from the com port 8, by way of the I/O device 5, system bus 7, and bus.cndot.memory controller 3, to be stored in the main memory 2. The necessary portions of the image data in the main memory 2 are written into the micro-processor 1 and the series of processes depicted in FIG. 13 are performed. The final image data are stored in the main memory 2 to be ready for the image accumulation task 57 and image rearranging task 55 (refer to FIG. 13), as well as being written into the frame buffer 9, by way of the bus.cndot.memory controller 3 and the video controller 4. The data in the frame buffer 9 are displayed on the monitor 6 under the control of the video controller 4. During the image processing process, various tasks such as reading out necessary data from the main memory and writing data temporarily into the main memory continue to be performed. The programs necessary to perform such tasks are also stored in the main memory, and necessary sections of the program are read into the microprocessor while the image processing processes are being carried out.
The image data are handled in units called a macro-block comprised roughly by 8.times.8 pixels, and are processed as an 8-bit matrix. The reverse quantizer task 52 and the reverse DCT task 53 are performed in matrix multiplications, and the signal addition task 54 performs matrix additions. These operations are performed by repeating the same types of computations, and computations can be made faster by using parallel processing devices. Recently, microprocessors having parallel processing pipelines are being applied to computers to enhance their image processing capability.
In the meantime, the variable-length encoding task 51 compares input data with the table and converts the input data to corresponding data. Because the bit length in the table are different depending on the encoding mode, it is not possible to find the start of the next word unless the previous word has been decoded. Therefore, the input signals must be examined serially, and consequently, they are not amenable to parallel processing. It can not be anticipated, therefore, that speed enhancement in the variable-length encoding process can be achieved through the use of parallel processing devices.
A review of the existing technology reveals a number of serious performance problems outlined in the following.
The first problem is that, in the conventional image processing technology, a microprocessor and memories are constituted by separate independent integrated circuits, and a bottleneck in the processing speed occurs in the slow process of data exchange between these two components of the computer system.
The reason is that, while independently configured ICs of the microprocessor and memories are needed to exchange a large volume of data for image processing need arising from pre-processing, intermediate processing and post-processing tasks, there is a limit to the number of I/O ports which can be provided in any given IC, so that the volume of data which can be exchanged to and from the IC is also limited.
The second problem is that, in the conventional computers, volume of image data which must be handled in a series of operations can sometimes be beyond the processing capacity of a given type of microprocessor.
The reason is that, although efforts are being made to provide an increased speed of processing by installing parallel processors to handle such tasks as reverse quantization process which are amenable to parallel processing, it is not possible to carry out decoding for the variable-length encoded words in a parallel processing device so that the rate of processing cannot be accelerated.
The third problem is that when the performance of the conventional image processing computers are improved, there is a tendency for the computer system to become higher priced.
The reason is that, because new devices, such as coprocessors, are added to the system, the price is increased by the cost of the added devices. Furthermore, if the low cost standardized components produced by mass production cannot be used for the revised computer system by adding the new devices, opportunity for reducing the system cost becomes severely limited.
Therefore, it is obvious that there is a need for a computer, using the capabilities of the standardized components, that can be produced at low cost and yet offers high image processing ability to handle a large volume of data.